1. Technical Field
The present invention relates generally to an NVRAM (nonvolatile random access memory) cell with a planar control gate, and more particularly pertains to an NVRAM cell with a planar control gate which is compatible with self-aligned silicide processes and also provides a planar surface for subsequent wiring processes.
2. Discussion of the Prior Art
Salicided (self-aligned silicided) processes do not work well, or work at all, when the polysilicon being silicided has a topography which includes large steps therein. Salicided processes do not work with conventional NVRAM cells because of the severe topography created when the wordline poly passes over the floating gates. In the case of NVRAM technology, the steps are large enough and steep enough to allow spacer formation on the top of the wordlines as they pass over the floating gate polysilicon. The spacer formation guarantees that silicide will not form continuously on the top of the wordline.